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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES All-In-One Synchronous Buck Driver One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Programmable Transition Delay Zero-Crossing Synchronous Drive Control Synchronous Override Control Undervoltage Lockout Shutdown Quiescent Current < 10 mA APPLICATIONS Mobile Computing CPU Core Power Converters Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations
VCC IN SD DLY
Dual MOSFET Driver with Bootstrapping ADP3415
FUNCTIONAL BLOCK DIAGRAM
ADP3415
UVLO BST DRVH SW OVERLAP PROTECTION CIRCUIT
VCC DRVL
DRVLSD GND
GENERAL DESCRIPTION
5V
VDC-IN
The ADP3415 is a dual MOSFET driver optimized for driving two N-channel FETs that are the two switches in the nonisolated synchronous buck power converter topology. The driver sizes are each optimized for performance in notebook PC regulators for CPUs in the 20-amp range. The high-side driver can be bootstrapped atop the switched node of the buck converter as needed to drive the upper switch, and is designed to accommodate the high voltage slew-rate associated with high-performance high-frequency switching. The ADP3415 has several features: an overlapping protection circuit (OPC) undervoltage lockout (UVLO) that holds the switches off until the driver is assured of having sufficient voltage for proper operation, a programmable transition delay, and a synchronous drive disable pin. The quiescent current, when the device is disabled, is less than 100 mA. The ADP3415 is available in a 10-lead MSOP package.
FROM DUTY RATIO MODULATOR FROM SYSTEM ENABLE CONTROL FROM SYSTEM STATE LOGIC
IN SD
VCC
BST DRVH VOUT
ADP3415
DRVLSD SW
DLY GND
DRVL
Figure 1. Typical Application Circuit
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADP3415-SPECIFICATIONS1 (T = 0 C to 100 C, V
A
CC
= 5 V, VBST = 4 V to 26 V, SD = 5 V, unless otherwise noted.)
Min Typ Max Unit
Parameter
Symbol
Conditions
SUPPLY (VCC) Supply Voltage Range Quiescent Current Shutdown Mode Operating Mode
4.15 ICCQ VSD = 0.8 V VSD = 5 V, No Switching 3.9
5.0 30 1.2 4.15 0.05
6.0 65 2 4.5
V A mA V V
UNDERVOLTAGE LOCKOUT(UVLO) VCCUVLO UVLO Threshold UVLO Hysteresis VCCHUVLO SYNCHRONOUS RECTIFIER SHUTDOWN (DRVLSD) Input Voltage High2 Input Voltage Low2 Propagation Delay2, 3 (See Figure 3) SHUTDOWN (SD) Input Voltage High2 Input Voltage Low2 INPUT (IN) Input Voltage High2 Input Voltage Low2 THERMAL SHUTDOWN(THSD) THSD Threshold THSD Hysteresis HIGH-SIDE DRIVER (DRVH) Output Resistance, DRVH-BST Output Resistance, DRVH-SW DRVH Transition Times3 (See Figure 4) DRVH Propagation Delay 3, 4 (See Figure 4) LOW-SIDE DRIVER (DRVL) Output Resistance, DRVL-VCC Output Resistance, DRVL-GND DRVL Transition Times3 (See Figure 4) DRVL Propagation Delay3, 4, 6 (See Figure 4) SW Transition Timeout6 Zero-Crossing Threshold DRVH TURN-ON DELAY TIMER Programmable Delay7 Delay Slope7
VIH VIL tpdlDRVLSD tpdhDRVLSD VIH VIL VIH VIL TSD THSD
2.0 VCC = 4.6 V, CLOAD(DRVL) = 3 nF 2.0 0.8 2.0 0.8 165 10 VBST - VSW = 4.6 V VBST - VSW = 4.6 V VBST - VSW = 4.6 V, CLOAD = 3 nF VBST - VSW = 4.6 V, VDLY = 0 V 10 1.5 .85 20 25 22 40 1.6 1 27 24 33 14 1 0 RDLY 100 k 100 k RDLY including open 0 RDLY 100 k 0 100 0 3.5 2 30 35 40 50 3 3 40 30 38 25 300 23 17 0.8 50 30
V V ns ns V V V V C C ns ns ns ns ns ns ns ns ns V
trDRVH, tfDRVH tpdhDRVH, tpdlDRVH VCC = 4.6 V VCC = 4.6 V trDRVL, tfDRVL tpdhDRVL, tpdlDRVL tSWTO VZC tDLY tDLY/RDLY
VCC = 4.6 V, CLOAD = 3 nF VCC = 4.6 V 5 100
1
100 s 200 s 1.2 ks/k
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Logic inputs meet typical CMOS I/O conditions for source current larger than 100 A. 3 Guaranteed by characterization. 4 For propagation delays, "tpdh" refers to the specified signal going high, "tpdl" refers to it going low. 5 Propagation delay measured until DRVL begins its transition. 6 The turn-on of DRVL is initiated after IN goes low by either V SW crossing a ~1 V threshold or by expiration of t SWTO. 7 This delay represents a programmable extension to the propagation delay of DRVH assertion (t PDH DRVH). The additional delay is a linear function of the range 0 RDLY 100 k delay resistor tied from DLY to GND if its value is the specified resistance. 8 The DLY pin may be grounded for no additional delay. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA ADP3415
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8
Mnemonic IN SD DRVLSD DLY VCC DRVL GND SW
Function TTL-Level Input Signal. Has primary control of the drive outputs. Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced low and the supply current (ICCQ)) is minimized as specified. Drive-Low Shutdown. When DRVLSD is low, DRVL is kept low. When DRVLSD is high, DRVL is enabled and controlled by IN and by the adaptive OPC function. High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-off of the lower FET to turn-on of the upper FET. Input Supply. This pin should be bypassed to GND with ~10 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET. Ground. Should be directly connected to the ground plane, close to the source of the lower FET. This pin should be connected to the buck switching node, close to the upper FET's source. It is the floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for the OPC function. Buck Drive. Output drive for the upper (buck) FET. Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holds this bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be a MLC type and should have substantially greater capacitance (e.g., ~20 ) than the input capacitance of the upper FET.
PIN CONFIGURATION 10-Lead Mini_SO Package (MSOP) (RM-10)
9 10
DRVH BST
ABSOLUTE MAXIMUM RATINGS*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . -2.0 V to +25 V SD, IN, DRVLSD to GND . . . . . . . . . . . . . -0.3 V to +7.3 V Operating Ambient Temperature Range . . . . . . 0C to 100C Operating Junction Temperature Range . . . . . . 0C to 125C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155C/W JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
IN 1 SD DRVLSD
2 3
10
BST
DRVH TOP VIEW 8 SW (Not to Scale)
9 7 6
ADP3415
DLY 4 VCC 5
GND DRVL
ORDERING GUIDE
Temperature Model ADP3415KRM-Reel ADP3415KRM-Reel7
Range 0C to 100C 0C to 100C
Package Description Mini_SO Package MSOP-10) Mini_SO Package (MSOP-10)
Package Option RM-10 RM-10
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PRELIMINARY TECHNICAL DATA ADP3415
5V D1 VDC-IN VCC VCC BIAS SD EN THERMAL SHUTDOWN
ADP3415
TSD
BST VCC DLY RDLY TURN ON DELAY DRVL 10% VCC UVLO TSD IN S Q S Q SW R R UVLO 4.15V DRVH DRVH CBST
S
Q
UVLO TSD
VCC DRVL
R GND TIME OUT DELAY DRVLSD
Figure 2. Functional Block Diagram
IN
DRVLSD 2.0V 0.8V tpdl DRVLSD tpdh DRVLSD
DRVL
Figure 3. DRVLSD Propagation Delay
IN
tpdlDRVL tfDRVL
tpdlDRVH
trDRVL
DRVL
tpdhDRVH
trDRVH
tfDRVH
VTH DRVH-SW
VTH
SW
tSWTO
1V
tpdhDRVL
Figure 4. Driver Switching Timing Diagram (Timing is referenced to the 90% and 10% points unless otherwise noted.)
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PRELIMINARY TECHNICAL DATA Typical Performance Characteristics-ADP3415
37
2V/DIV
35
VCC = 5V CLOAD = 3nF
DRVH
33 31 RISE
DRVL
TIME - ns
29 27
IN
25 FALL
20ns/DIV TIME - ns
VCC = 5V CLOAD = 3nF VSW = 0V
23 21
0
25
50
75
100
125
JUNCTION TEMPERATURE - C
TPC 1. DRVH Fall and DRVL Rise Times
TPC 4. DRVL Rise and Fall Times vs. Temperature
30
2V/DIV
28
DRVL
VCC = 5V CLOAD = 3nF FALL TIME
26
TIME - ns
DRVH
24 22 RISE TIME
IN
20
VCC = 5V CLOAD = 3nF RDLY = 0V TIME - ns
18 16
20ns/DIV
0
25
50
75
100
125
JUNCTION TEMPERATURE - C
TPC 2. DRVL Fall and DRVH Rise Times
TPC 5. DRVH Rise and Fall Time vs. Temperature
100 90 80 70
A
70 VCC = 5V TA = 25 C CLOAD = 3nF VCC = 5V TA = 25 C 60
50
PEAK CURRENT -
50 40 30 20 10 0 0 1 2 3 INPUT VOLTAGE - V 4 5
TIME - ns
60
DRVL 40
30
DRVH
20
10
1
2
3
4
5
6
7
8
9
10
LOAD CAPACITANCE - nF
TPC 3. Input Voltage vs. Input Current
TPC 6. DRVH and DRVL Rise Time vs. Load Capacitance
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PRELIMINARY TECHNICAL DATA ADP3415
52 VCC = 5V 47 CLOAD = 3nF 42 37 45 40 VCC = 5V TA = 25 C CLOAD = 3nF
tpdl DRVH
SUPPLY CURRENT - mA
35 30 25 20 15 10 5 0 200
TIME - ns
32 27 22 17
tpdl DRVL
12 7 2 0 25 50 75 100 JUNCTION TEMPERATURE - C 125
400
600 800 IN FREQUENCY - kHz
1000
1200
TPC 7. DRVH and DRVL Propagation Delay vs. Temperature
TPC 10. Current vs. Frequency
52 47 42 37 TIME - ns 32 27 22 17 12 7 1 2 3 4 7 5 6 LOAD CAPACITANCE - uF 8 9 10 DRVL VCC = 5V TA = 25 C
10.5 10.0 9.5
SUPPLY CURRENT - mA
9.0 8.5 8.0 7.5 7.0 6.5 6.0 0 25 50 75 100 JUNCTION TEMPERATURE - C 125 VCC = 5V fIN = 250kHz CLOAD = 3nF
DRVH
TPC 8. DRVH and DRVL Fall Time vs. Load Capacitance
TPC 11. Current vs. Temperature
182 162 142
VCC = 5V fIN = 200kHz CLOAD = 3nF OPEN DELAY PIN
122
TIME - ns
102 82 62 42 SHORTED TO GROUND 22 2 0 25 50 75 100 JUNCTION TEMPERATURE - C 125
TPC 9. tPDH DRVH vs. Temperature
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PRELIMINARY TECHNICAL DATA ADP3415
THEORY OF OPERATION
The ADP3415 is a dual MOSFET driver optimized for driving two N-channel FETs in a synchronous buck converter topology. A single duty ratio modulation signal is all that is required to command the proper drive signal for the high-side and the lowside FETs. A more detailed description of the ADP3415 and its features follows. Refer to the functional block diagram (Figure 3).
Drive State Input
The drive state input, IN, should be connected to the duty ratio modulation signal of a switch-mode controller. IN can be driven by 2.5 V-5.0 V logic. The FETs will be driven so that the SW node follows the polarity of IN.
Low-Side Driver
(after a propagation delay) but before Q2 can turn ON, the overlap protection circuit waits for the voltage at the SW pin to fall from V DC-IN to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2 will begin to turn ON. By waiting for the voltage on the SW pin to reach 1 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. There is, however, a timeout circuit that will override the waiting period for the SW pin to reach 1 V. After the timeout period has expired, DRVL will be asserted regardless of the SW voltage. To prevent the overlap of the gate drives during Q2's turn OFF and Q1's turn ON, the overlap circuit provides a programmable delay that is set by a resistor on the DLY pin. When IN goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit initiates a delay timer that is programmed by the external resistor RDLY. The delay resistor adds an additional specified delay. The delay allows time for current to commutate from the body diode of Q2 to an external Schottky diode, which allows turnoff losses to be reduced. Although not as foolproof as the adaptive delay, the programmable delay adds a safety margin to account for variations in size, gate charge, and internal delay of the external power MOSFETs.
Low-Side Driver Shutdown
The supply rails for the low-side driver, DRVL, are VCC and GND. In its conventional application it drives the gate of the synchronous rectifier FET. When the driver is enabled, the driver's output is 180 out of phase with the duty ratio input aside from OPC, propagation, and transition delays. When the driver is shut down or the entire ADP3415 is in shutdown or in under-voltage lockout, the lowside gate is held low.
High-Side Driver
The supply rail for the high-side driver, DRVH, is between the BST and SW pins, and is created by an external bootstrap supply circuit. In its conventional application it drives the gate of the (top) main buck converter FET. The bootstrap circuit comprises a Schottky diode, D1, and bootstrap capacitor, CBST. When the ADP3415 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. As the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When the input pin, IN, goes high, the high-side driver will begin to turn the high-side FET (Q1) ON by transferring charge from CBST to the gate of the FET. As Q1 turns ON, the SW pin will rise up to VDC-IN, forcing the BST pin to VDC-IN + VC(BST), which is enough gate to source voltage to hold Q1 ON. To complete the cycle, when IN goes low, Q1 is switched OFF as DRVH discharges the gate to the voltage at the SW pin. When the lowside FET, Q2, turns ON, the SW pin is held at ground. This allows the bootstrap capacitor to charge up to VCC again. The high-side driver's output is in phase with the duty ratio input. When the driver is in under-voltage lockout, the highside gate is held low.
Overlap Protection Circuit
The low-side driver shutdown (DRVLSD) allows a control signal to shut down the synchronous rectifier. This signal should be modulated by system state logic to achieve maximum battery life under light load conditions and maximum efficiency under heavy load conditions. Under heavy load conditions, DRVLSD should be high so that the synchronous switch is modulated for maximum efficiency. Under light load conditions, DRVLSD should be low to prevent needless switching losses due to charge shuttling caused by polarity reversal of the inductor current when the average current is low. When the DRVLSD input is low, the low-side driver stays low. When the DRVLSD input is high, the low-side driver is enabled and controlled by the driver signals as previously described.
Shutdown
For optimal system power management, when the output voltage is not needed, the ADP3415 can be shut down to conserve power. When the SD pin is high, the ADP3415 is enabled for normal operation. Pulling the SD pin low forces the DRVH and DRVL outputs low, turning the buck converter OFF, and reducing the VCC supply current to less than 40 A.
Undervoltage Lockout
The Overlap Protection Circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This prevents excessive shoot-through currents from flowing through both power switches and minimizes the associated losses that can occur during their ON-OFF transitions. The Overlap Protection Circuit accomplishes this by adaptively controlling the delay from Q1's turn OFF to Q2's turn ON, and by programming the delay from Q2's turn OFF to Q1's turn ON. To prevent the overlap of the gate drives during Q1's turn OFF and Q2's turn ON, the overlap circuit monitors the voltage at the SW pin. When IN goes low, Q1 will begin to turn OFF
The undervoltage lockout (UVLO) circuit holds both FET driver outputs low during VCC supply ramp-up. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of no greater than 1.5 V. The UVLO circuit waits until the VCC supply has reached a voltage high enough to bias logic level FETs fully ON, around 4.1 V, before releasing control of the drivers to the control pins.
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PRELIMINARY TECHNICAL DATA ADP3415
Thermal Shutdown
The thermal shutdown circuit protects the ADP3415 against damage due to excessive power dissipation. Under extreme conditions, high ambient temperature and high power dissipation, the die temperature may rise up to the thermal shutdown threshold of 165C. If the die temperature exceeds 165C, the thermal shutdown circuit will turn the output drivers OFF. The drivers remain disabled until the junction temperature has decreased by 10C, at which point the drivers are again enabled.
APPLICATION INFORMATION Supply Capacitor Selection
where QGATE is the total gate charge of the high-side FET, and VBST is the voltage droop allowed on the high-side FET drive. For example, the IRFR8503 has a total gate charge of about 15 nC. For an allowed droop of 150 mV, the required bootstrap capacitance is 100 nF. Use an MLC capacitor. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side FET. The bootstrap diode must also be able to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by:
I F ( AVG ) QGATE x f MAX
Delay Resistor Selection
(2)
For the supply input (VCC) of the ADP3415, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 10 F, MLC capacitor. Keep the ceramic capacitor as close as possible to the ADP3415. Multilayer ceramic (MLC) capacitors provide the best combination of low ESR and small size, and can be obtained from the following vendors: Murata Taiyo-Yuden Tokin
Bootstrap Circuit
where fMAX is the maximum switching frequency of the controller. The delay resistor, RDLY, is used to add an additional delay when the low-side FET drive turns off and when the high-side drive starts to turn on. The delay resistor programs a specified additional delay besides the 20 ns of fixed delay.
Printed Circuit Board Layout Considerations
GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP
www.murata.com www.t-yuden.com www.tokin.com
Use the following general guidelines when designing printed circuit boards: 1. Trace out the high current paths and use short, wide traces to make these connections. 2. The VCC bypass capacitor should be located as close as possible to VCC and GND pins.
The bootstrap circuit requires a charge storage capacitor, CBST, and a Schottky diode, D1, as shown in Figure 2. Selecting these components can be done after the high-side FET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 V. The capacitance is determined using the following equation:
CBST =
QGATE VBST
(1)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10-Lead Mini_SOIC Package (MSOP) (RM-10)
0.124 (3.15) 0.112 (2.84)
10
6
0.124 (3.15) 0.112 (2.84)
1 5
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0197 (0.50) BSC 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 6 SEATING 0.006 (0.15) 0.016 (0.41) PLANE 0 0.022 (0.56) 0.011 (0.28) 0.002 (0.05) 0.006 (0.15) 0.021 (0.53) 0.003 (0.08) 0.122 (3.10) 0.110 (2.79)
0.038 (0.97) 0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
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